Download e-book for kindle: 100 Power Tips for FPGA Designers by Evgeni Stavinov

By Evgeni Stavinov

This publication is a set of brief articles on numerous elements of FPGA layout: synthesis, simulation, porting ASIC designs, floorplanning and timing closure, layout methodologies, functionality, region and tool optimizations, RTL coding, IP middle choice, and so forth. The ebook is meant for procedure architects, layout engineers, and scholars who are looking to enhance their FPGA layout talents. either beginner and professional good judgment and engineers can locate bits of valuable info. This booklet is written by means of a practising FPGA common sense clothier, and features a lot of illustrations, code examples, and scripts. instead of supplying info appropriate to all FPGA proprietors, this ebook variation specializes in Xilinx Virtex-6 and Spartan-6 FPGA households. Code examples are written in Verilog HDL. All code examples, scripts, and tasks supplied within the publication can be found on accompanying web site:

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Tip #6 overviews some of the popular Lint tools. Resources [1] “Standard Gotchas: Subtleties in the Verilog and SystemVerilog Standards That Every Engineer Should Know”, by Stuart Sutherland. Published in the proceedings of SNUG Boston, 2006. pdf 15. Writing Synthesizable Code for FPGAs The Verilog language reference manual (LRM) provides a rich set of capabilities to describe hardware. However, only a subset of the language is synthesizable for FPGA. Even if a particular language structure is synthesizable, that doesn’t guarantee that the code will pass physical implementation for a specific FPGA.

FPGA architecture only supports 2-state values (logic ‘0’ and ‘1’), and synthesis tools will apply different rules to optimize ‘z’ and ‘x’ values during the synthesis process. That will cause a mismatch between synthesis and simulation results (also see Tip #59) and other side effects. Only use ‘z’ values during the implementation of tri-stated IO buffers. translate_on/translate_off compiler directives translate_off and translate_on directives instruct synthesis tools to ignore portions of a Verilog code.

Published in the proceedings of SNUG Boston, 1999. 16. Instantiation vs. Inference Instantiation and inference are two different methods of adding components to an FPGA design. Each method offers its advantages, but also has drawbacks. Component instantiation directly references an FPGA library primitive or macro in HDL. The main advantage of the instantiation method is that it provides a complete control of all the component features, and FPGA resources it will use. Also, instantiation makes it simpler to floorplan the component.

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100 Power Tips for FPGA Designers by Evgeni Stavinov

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