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If one is considering an input frequency, this could be converted to a phase by dividing by a factor of s, then it is converted to a phase. At the output, one would multiply by a factor of s to convert the output phase to a frequency. So both of these factors cancel out, which proves that the phase transfer functions and frequency transfer functions are the same. By considering the change in output frequency produced by introducing a test frequency at various points in the PLL loops, all of the transfer functions can be derived.

If the loop bandwidth is increased, then the lock time can be reduced in this way. The second, and more common, situation occurs when the discrete sampling rate of the phase detector is limiting the loop bandwidth. Recall that the loop bandwidth cannot be practically made much wider than 1/5th of the comparison frequency. If the comparison frequency is increased by a factor of FDEN, then the loop bandwidth can be increased. This is assuming that the spur levels are low enough to tolerate this increase in loop bandwidth.

If the comparison frequency is increased by a factor of FDEN, then the loop bandwidth can be increased. This is assuming that the spur levels are low enough to tolerate this increase in loop bandwidth. In some cases, the use of fractional N PLLs can actually lead to longer lock times. This is because the comparison frequency can be made high. If it is made more than about 100 times the loop bandwidth, then the lock time can be degraded due to a phenomenon called cycle slipping, which will be discussed later.

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CAS-CERN Accelerator School - Advanced Accelerator Physics (VOL 1)


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